1. Field of the Invention
This invention is for an electrical circuit that provides voltage gain by means of a differential current transfer.
2. Description of the Related Art
Voltage gain stages have been developed whose operation includes a differential current transfer. Such circuits are useful in operational amplifiers, comparators and other circuits in which a voltage level shifting function is accomplished by means of a differential current transfer.
A known circuit that performs this function is shown in FIG. 1. A differential input voltage V.sub.in is applied across the bases of a pair of input bipolar transistors Q1 and Q2. The transistors are illustrated as pnp devices, but the circuit can also be implemented with npn transistors. A current source I1 is connected to a positive voltage bus V+ and provides a current that is divided between the two transistors Q1, Q2 in accordance with the input voltage differential. The collectors of Q1 and Q2 are connected to a negative voltage bus V- through load resistors R1 and R2, respectively. The difference in the current magnitude supplied by Q1 and Q2 to their respective load resistors is the differential current output of the first stage. The circuit is designed to use this differential current in a second stage to produce an overall voltage gain.
The second stage is shown immediately to the right of Q2. It includes a Wilson current mirror, shown enclosed in dashed line 2, which supplies a pair of mirrored currents to bipolar transistors Q3 and Q4. The collector-emitter circuits of Q3 and Q4 are connected to supply current to R1 and R2, respectively. A common base bias is establish for Q3 and Q4 by a bias circuit consisting of current source I2, diode-connected transistor Q5 and resistor R3, all of which are connected in series between V+ and V-. The base of Q5 is connected in common with the bases of Q3 and Q4, so that the base bias voltage for the latter two transistors is equal to the sum of the base-emitter voltage across Q5 and the voltage across R3. I2 and R3 are selected so that the voltage across R3 is ideally equal to the voltages across R1 and R2.
The second stage output is taken from the collector of Q4 along line 4. An output stage is provided consisting of bipolar transistors Q6 and Q7 and resistor R4, all connected in series between V+ and V-. Output line 4 from the second stage is connected to the base of Q6, while the base of Q7 is biased in common with Q3, Q4 and Q5. The final circuit output V.sub.o is taken from the connection between the emitter of Q6 and the collector of Q7, both of which are illustrated as npn transistors.
In the ideal operation of this circuit, the difference in current flowing through Q3 and Q4 is equal to the difference in current flowing through Q2 and Q1, so that the total current flowing through R1 (the sum of the currents from Q1 and Q3) equals the total current flowing through R2 (the sum of the currents from Q2 and Q4). R1 and R2 would normally be equal value impedances, so that the voltages across R1 and R2 would ideally be equal.
The circuit of FIG. 1 suffers from an inaccuracy in the current transfer under dynamic input conditions. Assume first that the circuit is balanced, with the total current through R1 (supplied by Q1 and Q3) equal to the total current through R2 (supplied by Q2 and Q4). Then assume that the relative input voltage to Q1 goes down, resulting in a shift in the current supplied by source I1 away from Q1 and towards Q2. As a result, the current through Q3 increases and the current through Q4 decreases so that the total currents through R1 and R2, and the voltage drops across these resistors, attempt to remain constant. However, as the collector-emitter currents through Q3 and Q4 change, the base-emitter voltages of these transistors will also vary, since they are operating unsaturated. As a result, the currents from Q3 and Q4 will depart from their desired values, the currents through R1 and R2 will not be equal, and the current transfer from the first to the second stage will not be 100%.
The present invention seeks to improve the dynamic current transfer operation of the FIG. 1 circuit. There is another prior circuit, shown in FIG. 2, that is relevant to the invention. The FIG. 2 circuit, however, is for steady state operation and serves an entirely different function. The circuit is a dual output current source, in which dual output currents are supplied to load resistors R5 and R6 by current source bipolar transistors Q8 and Q9, respectively. A bias circuit for Q8 and Q9 is formed by a circuit consisting of current source I3, diode-connected transistors Q10 and Q11, and resistor R7, all connected in series between positive and negative buses V+ and V-. Q8 and Q9 have a common base connection with Q10, and therefore are proportionately mirror the current transmitted through Q10 from I3. The emitters of npn devices Q8 and Q9 are connected through resistors R8 and R9 to V-by a cross-coupled cascode circuit consisting of npn transistors Q12 and Q13, with the collector-emitter circuit of Q12 connected between the emitter of Q8 and R8, and the collector-emitter circuit of Q13 connected between the emitter of Q9 and R9. Q12 and Q13 are cross-coupled by connecting the base of each to the collector of the other.
Without the Q12/Q13 circuit, it is necessary to adjust both the sizes of R8 and R9 and the emitter areas of Q8 and Q9 to adjust the output currents through R5 and R6. The addition of cross-coupled transistors Q12 and Q13 eliminates the need to adjust the emitter areas of Q8 and Q9, keeping the ratio of the output currents through R5 and R6 in a substantially constant proportion to the R9/R8 ratio. Changes in the relative steady state output currents can be made by changing the values of R8 and/or R9, without modifying the emitter areas of Q8 and Q9. This circuit is not designed, however, for a dynamic mode in which the ratio of the output current through R5 and R6 is continually changing. Rather, once the output current ratio is set it remains fixed, and will not change unless the resistors R8 and/or R9 are modified.